1. Field of the Invention
The present invention relates to a semiconductor package, more specifically, to a semiconductor package integrating multiple memory chips in an independent encapsulant.
2. Background of the Invention
For the rapidly increasing processing speed of the central processing unit (CPU), the capacity of the memory chips required is becoming relatively higher and higher, of which the speed quadrupling every two or three years. From the past 4 MB DRAM to the current 256 MB DRAM in mass production, the memory chip plays an indispensable role in the whole computer architecture. In order to produce a memory chip with higher capacity, the wafer FAB is required to continuously improve the processing ability and to purchase production equipments of higher cost and precision.
FIG. 1 is a conventional JEDEC (Joint Electronic Device Engineering Council) TSOP54 (Thin Small Outline Package 54 pins) stacking memory chip package 10. The stacking package 10 is to overlap the encapsulant of the individual TSOP54 package 11 up-and-down, and be bonded together, so as to obtain a multiple of memory chip capacity in the same occupied areas. The leadframes 13 of the TSOP54 package 11 are bonded together with the integrated pins 14 for surface mounting, wherein the integrated pins 14 are used to electrically connect the individual leadframes 13. Finally, the integrated pins 14 are responsible for transmitting and receiving the electrical signals from the external system. Each of the encapsulants 12 is provided with a memory chip 15 therein, and electrically connected with the leadframes 13 inside the encapsulant by the metal bonding wires 16.
As described, it is known that the conventional technique has several problems as follows:    (1) Every memory chip 15 needs to be independently packaged, and then stacked and bonded together. Therefore, there are more processing steps overall and longer time is needed. Also, the cost of the packaging material for the overall usage adds up to the cost of the manufacturing material of each package.    (2) Because the encapsulant is stacked and bonded in vertical direction, it can only save the occupied planar footprint, but the total thickness is too big to be applied in a device with narrow space, such as a notebook computer.    (3) The electrical signals are connected to each TSOP 54 package 11 through external integrated pins, so that the signal transmission path is longer and the resistance for the path is larger, which is disadvantageous to high-speed transmission and data access.